Fully automated simulation computer programs have been quite successful at modeling on-chip interconnect in digital circuits. RF circuits, however, provide an extra set of challenges that make full automation difficult and impractical. The need for accurate inductance modeling and coupled substrate modeling are two of the difficulties. Furthermore, a more detailed knowledge of the circuit (such as which lines compose a differential pair) is often required. Rather than start from a nearly finished layout, the problem definition, in this invention, starts and ends with the user. Lower level functionality is then provided to minimize the tedium, to make experimentation of the model parameters and layout easier, and to help the user best understand the effect of each line and each parasitic on the circuit. As important, an equivalent compact model is provided without excessive generation time and without severely increasing the circuit simulation time.
As stated above, fully automated computer programs have been quite successful at simulating on-chip interconnect in digital circuits. In a typical scenario, the substrate is doped highly enough that the Silicon surface can be approximated as a conductive plane at the ground potential, and interconnect inductance does not need to be modeled (Although, this approximation becomes less accurate as digital circuits approach RF speeds). This leaves only inter-line and line-substrate capacitance to be modeled. Due to shielding, only short-range capacitive interactions need to be considered; and this makes it easy to partition a complicated layout with many lines into a larger number of smaller groups of lines for simulation.
In modeling inductance, however, it is not a good approximation to assume that distant lines are shielded by currents in metallization between these lines. Even worse, by neglecting mutual inductances smaller than some arbitrary cutoff, it is easy to run into situations where the combined model of the remaining inductances correspond to situations where energy conservation is violated (or to cases such that an effective subcircuit exists with negative inductance). To be safe, a fully-automated program is almost forced to avoid this scenario by adding the full inductance matrix to the circuit simulation. This is possible, but this normally makes the circuit simulations prohibitively slow.
Similarly, substrate coupling is also difficult to partition due to long-range interactions which have a typical length scale on the order of the wafer thickness (since the die-attach acts a ground plane). Since nearby lines (closer than the wafer thickness) “compete for fringing space,” modeling each line separately for its admittance to the die attach would severely overestimate the admittance. The presence of each line alters the substrate interactions between the remaining lines. So, again, it is difficult to make the problem small in an automatic way. Unlike inductances, admittances smaller than an arbitrary cutoff can be safely omitted from the circuit simulation. However, since a matrix inversion is necessary to obtain the substrate coupling, the model generation step becomes prohibitively slow when the matrix becomes too large.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a relatively accurate and efficient computer simulation line modeling tool.